1. Field
Various features relate to integrated circuits, and more specifically, to using dynamic voltage scaling and frequency scaling techniques to enhance integrated circuit identification systems that use circuit-delay based physical unclonable functions.
2. Background
In the era of pervasive computing a lot of security issues exist related to software copyright protection, counterfeit ICs (i.e., chips), and system reliability. Software protection is a family of computer security techniques that are used to prevent the unauthorized copying of software. In other words, software must be able to determine whether the user is properly licensed to use it, and run only if this is the case. Another problem related to software protection is how to identify whether the chip or platform, on which the software is running, is a counterfeit chip. Counterfeit chips have proliferated throughout the industry and are a risk to the electronics supply chain. The product fallout from counterfeit semiconductors can range from small problems like dropped calls to much larger issues such as airplane crashes. Consequently, identifying and restricting the usage of counterfeit chips in the electronics supply chain is vital.
An on-chip Physical Unclonable Function (PUF) is a chip-unique challenge-response mechanism exploiting manufacturing process variations inside ICs. PUFs provide a mechanism to uniquely identify a hardware device based on intrinsic variations of physical components. When multiple chips are manufactured, the complex semiconductor process introduces slight variations that are beyond the control of the designer. For instance, even if two chips are manufactured from the same silicon wafer, circuit components (e.g., transistors) designed to be the same will probably differ in their silicon level features (e.g., gate length, threshold voltage value, gate oxide thickness, etc.) by microscopic amounts that may seem trivial. However, since these unique characteristics are uncontrollable and inherent to the physical device, quantifying them can produce an intrinsic identifier. Several different types of PUFs have been proposed based on exploration and analysis of silicon variations in circuit delays, such as ring oscillator based PUFs, arbiter PUFs, and path-delay analysis based PUFs. A PUF circuit receives a challenge as an input, and based on the physicals differences described above, the same PUF circuit may generate different response values in different chips.
FIG. 1 illustrates a schematic block diagram of one example of a circuit-delay based PUF circuit 102 found in the prior art. The specific PUF circuit 102 shown is commonly known as a ring oscillator PUF. A plurality of ring oscillators (ROs) 104 may be concurrently enabled and their outputs are sent to two or more switches (multiplexers) 106, 108. Notably, the ROs and other components are supplied with a static supply voltage 119 (e.g., nominal supply voltage or a higher “stress” supply voltage). A challenge serves as input to each switch 106, 108, which causes each switch 106, 108 to then select a single RO from among the plurality of ROs 104. The challenges sent to the switches 106, 108 are designed such that each switch 106, 108 selects a different RO. The selected ROs each have a slightly different resonating frequency associated with them due to slight semiconductor-level manufacturing variations, even though each may have been manufactured to be identical. The PUF output (response) is generated by a pair-wise comparison 114 of these selected ring oscillators' frequencies as measured/stored by the counters 110, 112. For example, if the first counter 110 detects a higher frequency than the second counter 112, then a logical “1” may be generated, otherwise a logical “0” may be generated. In this fashion, the comparisons made represent a challenge/response mechanism where the chosen RO pair is the challenge and the RO frequency comparison result is the response. The same challenge issued to different yet (almost) identically manufactured chips will lead to different response values. This in turn helps identify one chip from another even though the chips may have been manufactured to be the same.
One problem with circuit-delay based PUFs is high power consumption. The RO based PUF 102 described above, as well as other types of circuit-delay based PUFs, operate using static supply voltages (e.g., nominal supply voltage or higher “stress” supply voltage) and may have relatively high operating frequencies. For instance, in ring oscillator based PUF approaches, the oscillation frequency can be several hundred MHz in typical designs even with relatively less advanced technology nodes (e.g. 90 nm), and the corresponding power consumption cannot be ignored. As another example, in path-delay analysis based PUFs, under typical supply voltages the clock needed to analyze the max operating frequency of each data path can be in the GHz range, which is difficult to be generate accurately in small frequency steps and may also consume significant power.
Another problem with circuit-delay based PUFs is the large circuit area overhead needed to implement them. In order to get a sufficient amount of bits to generate a chip ID, many replicated circuit units (e.g., a myriad of ring oscillator pairs) may be needed. Each of these circuit units occupies valuable area on the active surface of an IC, which may be otherwise used for other valuable modules such as memory or processing logic.
Thus, there exists a need to improve circuit-delay based PUFs so that they consume less power and less area, yet also still provide the same level of security (e.g., still provide the same encryption strength and number of identifier/key bits).